1. Field of the Invention
The present invention relates to an error correction decoder, more particularly to an error correction decoder for cyclic codes.
2. Description of the Related Art
Nowadays, development of digital storage technology and communication technology has resulted in relatively high speed of data access and transmission. However, since transmission media and channels are easily corrupted by interference during data access and transmission, error detection and correction has become more and more significant. Generally, error-correcting codes are used in existing satellite communication systems, digital televisions, various digital audio-video storage media, and the like for enhancing reliability of data access and transmission. In the error-correcting codes, application of a cyclic code is not uncommon.
A conventional error correcting method includes the steps of: receiving a signal; determining a plurality of syndromes based upon the received signal; using Berlekamp-Massey Algorithm to determine an error locator polynomial and an error magnitude polynomial based upon the syndromes; performing Chien search with the error locator polynomial and the error magnitude polynomial to determine at least one error position and an error correction value corresponding to the error position; and performing error correction upon the received signal. Theoretical bases of the conventional error correcting method are described in “The Art of Error Correcting, Robert H. et al., 2006” and “Fundamentals of Error-Correcting Codes, W. Cary Huffman and Vera Pless, 2003.”
However, the conventional error correcting method takes relatively more time and is more complex since it involves complex calculation for obtaining the error locator polynomial and the error magnitude polynomial and Chien search. The conventional error correcting method would not result insignificant problems or time delay in the past since the rate of data access and transmission then are relatively low. However, since performance and transmission rate of current computer systems are greatly enhanced, a large number of circuits and an increased speed for processing data are currently required to complete decoding procedure within a desired time limit. Unfortunately, the cost of hardware will increase, and consumed power of the systems will rise.